SDI Audio Intel FPGA IP User Guide

ID 683333
Date 12/15/2021

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Document Table of Contents

3.1. SDI Audio Embed IP Core

The SDI Audio Embed Audio IP core embeds audio into the SD-, HD-, and 3G-SDI video standards.

The format of the embedded audio is in accordance with the following standards:

  • SMPTE272M-ABCD standard for SD-SDI
  • SMPTE299M standard for HD-SDI
  • SMPTE299M standard for 3G-SDI (provisional)

This IP core supports AES audio format for 48-kHz sampling rate

This figure shows a block diagram of the SDI Audio Embed IP core.

Figure 1. SDI Audio Embed IP Core Block Diagram

The SDI Audio Embed IP core embeds up to 16 channels or 8 channel pairs. The input audio can be any of the sample rates permitted by the SMPTE272M-ABCD and SMPTE299M standards; synchronous to the video. If you want to embed audio pairs together in a sample audio group, the audio pairs must be synchronous with each other.

The SDI Audio Embed IP core consists of the following components:

  • An encrypted audio embedder core
  • A register interface block that provides support for an Avalon-MM control bus
The audio embedder accepts the audio in AES format, and stores each channel pair in an input FIFO buffer. As the embedder places the audio sample in the FIFO buffer, it also records and stores the video clock phase information.

When accepting the audio in AES format, the SDI Audio Embed IP core does one of the following operations:

  • maintains the channel-status details
  • replaces the channel-status details with the default or the RAM versions