BCH IP Core: User Guide

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ID 683320
Date 2/13/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the BCH IP Core 2. BCH IP Core Getting Started 3. BCH IP Core Functional Description 4. Document Revision History A. BCH IP Core Document Archive
1. About the BCH IP Core x
1.1. Intel® DSP IP Core Features 1.2. BCH IP Core Features 1.3. DSP IP Core Device Family Support 1.4. BCH IP Core Release Information 1.5. DSP IP Core Verification 1.6. BCH IP Core Performance and Resource Utilization
2. BCH IP Core Getting Started x
2.1. Installing and Licensing IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing IP Cores x
2.1.1. OpenCore Plus IP Evaluation 2.1.2. BCH IP Core OpenCore Plus Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. BCH IP Core Functional Description x
3.1. BCH IP Core Encoder 3.2. BCH IP Core Decoder 3.3. BCH IP Core Parameters 3.4. BCH IP Core Interfaces and Signals
3.4. BCH IP Core Interfaces and Signals x
3.4.1. Avalon-ST Interfaces in DSP IP Cores
1. About the BCH IP Core
2. BCH IP Core Getting Started
3. BCH IP Core Functional Description
4. Document Revision History
A. BCH IP Core Document Archive

2.1.1. Intel® FPGA IP Evaluation Mode

The free Intel® FPGA IP Evaluation Mode allows you to evaluate licensed Intel® FPGA IP cores in simulation and hardware before purchase. Intel® FPGA IP Evaluation Mode supports the following evaluations without additional license:
  • Simulate the behavior of a licensed Intel® FPGA IP core in your system.
  • Verify the functionality, size, and speed of the IP core quickly and easily.
  • Generate time-limited device programming files for designs that include IP cores.
  • Program a device with your IP core and verify your design in hardware.

Intel® FPGA IP Evaluation Mode supports the following operation modes:

  • Tethered—Allows running the design containing the licensed Intel® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel® Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel® Quartus® Prime software, and requires no Intel® Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
  • Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel® Quartus® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.

When the evaluation time expires for any licensed Intel® FPGA IP in the design, the design stops functioning. All IP cores that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.

You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.

Figure 2.  Intel® FPGA IP Evaluation Mode Flow
Note: Refer to each IP core's user guide for parameterization steps and implementation details.

Intel® licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel® FPGA IP cores that require a production license, before generating programming files that you may use for an unlimited time. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Self-Service Licensing Center or contact your local Intel FPGA representative.

The Intel® FPGA Software License Agreements govern the installation and use of licensed IP cores, the Intel® Quartus® Prime design software, and all unlicensed IP cores.

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