BCH IP Core: User Guide

ID 683320
Date 2/13/2017

3.2. BCH IP Core Decoder

When the decoder receives the encoded codeword, it uses the check symbols to detect errors and correct them.

The received encoded codeword may differ from the original codeword due to the noise in the channel. The decoder detects errors using several polynomials to locate the error location and the error value. When the decoder obtains the error location and value, the decoder corrects the errors in a codeword, and sends the codeword to the output.

If e<=t, the IP core can correct errors; if e > t, you see unpredictable results.
Figure 7. Decoder Timing

The codeword starts when you assert the in_valid signal and the in_startofpacket signal.The decoder accepts the data at in_data as valid data. The codeword ends when you assert the in_endofpacket signal. For a 1-channel codeword, assert the in_startofpacket and in_endofpacket signals for one clock cycle. When the decoder deasserts the in_ready signal, the decoder cannot process any more data until it asserts the in_ready signal again.

At the output, the operation is identical. When the decoder asserts the out_valid signal and the out_startofpacket signal, the decoder provides valid data on out_data. The decoder asserts the out_startofpacket signal and the out_endofpacket signal to indicate the start and end of a codeword. The decoder automatically detects and corrects errors in a codeword and asserts the out_error signal when it encounters a non-correctable codeword. The decoder outputs the full codeword including the check symbols, which you should remove.

The ready signal indicates that the decoder can accept an incoming stream. On clk rising edge, if the encoder ready signal is high, send input data stream via data_in and assert load high to indicate valid input data. When valid_out is asserted high, the output decoded word is valid at the data_out port. The number_errors shows the number of errors the IP core detects. At the first clock cycle where the output data is valid, sop_out is asserted high for only one cycle, indicating the start of output packet. The IP core has forward and back pressure, which you controll with the ready signal and sink_ready signal. Assert the sop_in and eop_in signals correctly at the clock cycle, i.e. the first and last clock cycle of the input codeword.