BCH IP Core: User Guide

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ID 683320
Date 2/13/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the BCH IP Core 2. BCH IP Core Getting Started 3. BCH IP Core Functional Description 4. Document Revision History A. BCH IP Core Document Archive
1. About the BCH IP Core x
1.1. Intel® DSP IP Core Features 1.2. BCH IP Core Features 1.3. DSP IP Core Device Family Support 1.4. BCH IP Core Release Information 1.5. DSP IP Core Verification 1.6. BCH IP Core Performance and Resource Utilization
2. BCH IP Core Getting Started x
2.1. Installing and Licensing IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel FPGA IP Cores 2.5. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing IP Cores x
2.1.1. OpenCore Plus IP Evaluation 2.1.2. BCH IP Core OpenCore Plus Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. BCH IP Core Functional Description x
3.1. BCH IP Core Encoder 3.2. BCH IP Core Decoder 3.3. BCH IP Core Parameters 3.4. BCH IP Core Interfaces and Signals
3.4. BCH IP Core Interfaces and Signals x
3.4.1. Avalon-ST Interfaces in DSP IP Cores
1. About the BCH IP Core
2. BCH IP Core Getting Started
3. BCH IP Core Functional Description
4. Document Revision History
A. BCH IP Core Document Archive

3.3. BCH IP Core Parameters

Table 7.  Parameters
Parameter Legal Values Default Value Description
BCH module Encoder or Decoder Encoder Specify an encoder or a decoder.
Number of bits per symbol (m) 3 to 14 (encoder or 6 to 14 (decoder) 14 Specify the number of bits per symbol.
Codeword length (n) parity_bits+1 : 2m-1 8,784 Specify the codeword length. The decoder accept a new symbol every clock cycle if 6.5R < N. If N>=6.5R+1, the decoder shows continuous behavior.
Error correction capacity (t) Range derived from m. For the decoder, the wizard caps the range between 8 and 127. 40 Specify the number of bits to be corrected.
Parity bits – 560 Shows the number of parity bits in the codeword. The wizard derives this parameter from t.
Message length (k) – 8,224 Shows the number of message bits in the codeword. The wizard derives this parameter from t and n.
Primitive polynomial – 17,475 Shows the primitive polynomial. derived from the choice of m.
Parallel input data width Encoder: 1 to min(parity_bits, k-1). Decoder:
  • d < floor(n*3/14)
  • d < floor(n/floor[2*log2(2*t)])
20 The number of bits to input every clock cycle.
Level Two Title