Intel® Quartus® Prime Pro Edition Settings File Reference Manual
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Visible to Intel only — GUID: QSF-STA_AUTO_UPDATE_TIMING_NETLIST
Ixiasoft
Visible to Intel only — GUID: QSF-STA_AUTO_UPDATE_TIMING_NETLIST
Ixiasoft
STA_AUTO_UPDATE_TIMING_NETLIST
Directs the Timing Analyzer to automatically create the timing netlist, read SDC constraints, and update the timing netlist whenever this project is opened in an interactive Timing Analyzer session.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name STA_AUTO_UPDATE_TIMING_NETLIST <value>
Default Value
On