Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/12/2022
Public

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SYNTH_GATED_CLOCK_CONVERSION

Automatically converts gated clocks in the design to use clock enable pins if clock enable pins are not used in the original design. Clock gating logic can contain AND, OR, MUX, and NOT gates. Turning on this option may increase memory use and overall run time. You must use the Timing Analyzer for timing analysis, and you must define all base clocks in Synopsys Design Constraints (SDC) format.

Type

Boolean

Device Support

  • Agilex 7
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Intel® Stratix® 10

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax


set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION -entity <entity name> <value>
set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION -to <to> -entity <entity name> <value>
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION <value>

Default Value

Off

Example


set_global_assignment -name synth_gated_clock_conversion on
set_instance_assignment -name synth_gated_clock_conversion on -to foo