Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 12/12/2022
Public

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SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES

Allows the Compiler to skip the fitting stage during smart recompilation when design changes may affect timing requirements. This option is available only for changes to Cyclone, Stratix, and Stratix GX PLL parameters, and Stratix GX gigabit transceiver block (GXB) parameters.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Syntax


set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES <value>

Default Value

Off