Mailbox Client Intel® FPGA IP User Guide

ID 683290
Date 12/04/2023
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1.3.2. Avalon® Memory-Mapped Interface

The Avalon® memory-mapped interface is standard memory-mapped interface. For detailed definitions of these signals, refer to the Avalon® Memory-Mapped Interface chapter in the Avalon® Interface Specifications.

Table 3.   Avalon® Memory-Mapped Interface
Signal Role Width Direction Description
avmm_address 4 Input Avalon® memory-mapped interface address.
avmm_write 1 Input Avalon® memory-mapped interface write request.
avmm_read 1 Input Avalon® memory-mapped interface read request.
avmm_writedata 32 Input Avalon® memory-mapped interface write data bus.
avmm_readdata 32 Output Avalon® memory-mapped interface read data bus.
avmm_readdatavalid 1 Output Avalon® memory-mapped interface read data valid.
avmm_waitrequest 1 Output Avalon® memory-mapped interface wait request.