Mailbox Client Intel® FPGA IP User Guide

ID 683290
Date 12/04/2023
Public
Document Table of Contents
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1.4. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface

Table 5.   Avalon® Memory-Mapped Interface
Offset (word) R/W 31 30:2 1 0
Base address + 0 W Command
Base address + 1 W Command last word (eop)
Base address + 2 R Command FIFO empty space
Base address + 3 N/A Reserved
Base address + 4 N/A Reserved
Base address + 5 R Response data
Base address + 6 R Response FIFO fill level EOP SOP
Base address + 7 R/W Interrupt enable register (IER)
Base address + 8 R Interrupt status register (ISR)
Base address + 9 R/W Timer 1 enable Timer 1 period
Base address + 10 R/W Timer 2 enable Timer 2 period