F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.06 24.1 9.3.0
  • Updated Clock Pin Output for FGT Designs table.
  • Updated RX DL Shim Wrapper section.
  • Updated Analog Parameters section.
2024.04.01 24.1 9.3.0
  • Updated Hardware and Software Requirements section.
  • Updated the following tables:
    • Clock Pin Output for FGT Designs
    • Error Condition Behavior
  • Added the following sections:
    • Deterministic Latency
    • SYSREF Pulse Generator
    • TX DL Shim Wrapper
    • RX DL Shim Wrapper
    • Deterministic Latency Design Considerations
2023.10.02 23.3 9.1.0
  • Updated the product family name to "Intel Agilex 7."
  • Added information about Device Speed Grade Support.
  • Added Riviera-PRO* simulator in Table: Testbench Simulation Scripts and in Hardware and Software Requirements section.
  • Added Analog Parameters section.
  • Added reg_write <avmm2_address> <desired_value>, reg_read <avmm2_address>, proc_avmm1_write <avmm1_address> <desired_value> and proc_avmm1_read <avmm1_address> commands in Table: System Console Commands for Hardware Testing.
  • Added information for Riviera-PRO* simulator and updated file directories in Compiling and Simulating the Design section.
  • Updated the following figures:
    • Example Design Tab
    • Directory Structure for Agilex™ 7 F-Tile Serial Lite IV Design Example
    • Example of Hardware Design Example Test Result in System Console
    • MAC and PCS Tab
2022.10.14 22.3 7.0.0
  • Updated Table: Design Example Components.
    • Updated description for the F-Tile Serial Lite IV Intel FPGA IP component.
  • Updated Hardware and Software Requirements.
  • Updated Table: Parameters in the Example Design Tab.
    • Updated description for the Select Board parameter.
  • Updated Directory Structure to add new folder.
  • Updated Figure: Directory Structure for Intel Agilex F-Tile Serial Lite IV Design Example.
    • Added new folder, ed_hwtest.
    • Updated folders, ed_sim and ed_synth.
  • Updated the steps in Compiling and Testing the Design.
  • Updated the transceiver data rates in Features.
  • Updated Table: System Console Commands for Hardware Testing.
  • Added Figure: Steps to perform Hardware Testing.
  • Updated the steps in Setting Up and Running the Toolkit.
  • Updated Figure: Setting JTAG Master.
  • Updated Toolkit GUI Setting.
    • Corrected PHY to PCS.
    • Updated steps.
  • Updated Figure: MAC and PCS Tab.
  • Updated Figure: Traffic Statistics Tab.
  • Updated F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide Archives.
2021.12.13 21.4 3.0.0
  • Added a footnote to the supported transceiver data rates in Features.
  • Added a new topic—Hardware Testing.
  • Updated topic title Software Requirements to Hardware and Software Requirements and added hardware testing.
  • Updated Figure: Example Design Tab.
  • Updated the steps in Compiling and Testing the Design.
  • Updated the command for ModelSim* and QuestaSim* simulators in Table: Testbench Simulation Scripts.
  • Updated Table: Parameters in the Example Design Tab to include the Agilex I-Series Transceiver-SoC Development Kit option under the Select Board parameter.
2021.10.22 21.3 3.0.0
  • Updated Software Requirements.
  • Corrected the steps in Compiling and Simulating the Design.
  • Updated Table: Testbench Simulation Scripts to include information for VCS* MX and QuestaSim* simulators.
2021.08.18 21.2 2.0.0 Initial release.
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