F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.5. Error Handling

The F-Tile Serial Lite IV IP detects error conditions and the behaviors in response to these error conditions.

Table 13.  Error Condition BehaviorIn this table, N represents the number of lanes.
Signal Width Location Direction Clock Domain Error Indication
tx_error 5 Top-level signal Output tx_core_clkout Not used.
rx_error

(N*2*2)+3 (PAM4 mode)

(N*2)*3 (NRZ mode)

Top-level signal Output rx_core_clkout

When asserted, indicates an error condition on the RX datapath.

  • [(N*2+2):N+3] = Indicates PCS error for a specific lane.
  • [N+2] = Indicates alignment error. Re-initialize lane alignment if this bit is asserted.
  • [N+1]= Indicates data is forwarded to the user logic when user logic is not ready.
  • [N] = Indicates loss of alignment.
  • [(N-1):0] = Indicates the data contains CRC error.

tx_adaptation_fifo_full

1

Top-level TX DCFIFO signal

 Output TX user clock This vector indicates the write domain TX buffer is full and cannot accept data.

rx_adaptation_fifo_full

1

Top-level TX DCFIFO signal

 Output TX user clock This vector indicates the write domain RX buffer is full and cannot accept data.

readfull

1

Top-level RX DCFIFO signal

 Output RX user clock This vector indicates the read domain buffer is full and cannot accept data.
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