F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

ID 683287
Date 12/13/2021
Public

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2.3.1. Design Example Parameters

The F-Tile Serial Lite IV Intel® FPGA IP parameter editor includes an Example Design tab for you to specify parameters before generating the design example.
Figure 4. Example Design Tab
Table 4.  Parameters in the Example Design Tab
Parameter Description
Generate Files for

The IP generates the necessary design example files for simulation and compilation.

Simulation—select this option to generate the necessary design simulation files.

Synthesis—select this option to generate the necessary design synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Edition software for hardware testing.

Generate Files for Synthesis

When selected, the IP generates the synthesis files. Use these files to compile the design in the Intel® Quartus® Prime Pro Edition software for hardware testing.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is grayed out, there is no supported board for the options that you select.

Agilex I-Series Transceiver-SoC Development Kit: This option allows you to test the design example on the selected Intel® Agilex™ I-Series Transceiver-SoC development kit.

No Development Kit: This option excludes the hardware aspects for the design example.

Change Target Device Select a different device grade for Intel® FPGA IP development kit. For device-specific details, refer to the device datasheet on the Intel FPGA website.