F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

ID 683287
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 3.0.0

This document provides features, usage guidelines, and functional description of the F-Tile Serial Lite IV Intel® FPGA IP design examples using F-tile transceivers in Intel® Agilex® devices.

Intended Audience

This document is intended for the following users:
  • Design architects to make IP selection during system level design planning phase.
  • Hardware designers when integrating the IP into their system level design.
  • Validation engineers during system level simulation and hardware validation phase.

Acronyms and Glossary

Table 1.  Acronym List
Acronym Expansion
CW Control Word
RS-FEC Reed-Solomon Forward Error Correction
PMA Physical Medium Attachment
TX Transmitter
RX Receiver
PAM4 Pulse-Amplitude Modulation 4-Level
NRZ Non-return-to-zero
PCS Physical Coding Sublayer
MII Media Independent Interface
XGMII 10 Gigabit Media Independent Interface