F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software and Hardware Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.7.2. Toolkit GUI Settings

The F-Tile Serial Lite IV IP toolkit offers an easy-to-manage user interface.
The F-Tile Serial Lite IV IP toolkit user interface has three tabs.
  • The MAC and PHY tab implements various control and status registers (CSR) for both the hardened custom PCS core and the MAC soft logic.
  • The Traffic Statistics tab implements various Control and Status Registers (CSR) for the Demo Management module to configure the traffic generator and checker.
  • The Help tab provides useful next-step troubleshooting information based on the assertion and deassertion of specific status registers or output ports if any errors happen after the link initialization is executed.

The MAC and PHY tab shows a step-by-step guide for link initialization and real-time status monitoring of a F-Tile Serial Lite IV IP link.

The toolkit continuously reads and displays all of the essential status registers related to the F-Tile Serial Lite IV IP link after you execute the following stages:

  1. Click Assert Full System Reset to perform a full system reset.
  2. Click Link Initialization to perform link initialization.
  3. Click Read PCS Status to poll all corresponding status registers and output ports from both hardened custom PCS and MAC soft logic.
Figure 15. MAC and PHY Tab
Note: The toolkit user interface changes dynamically to illustrate each execution stage.

In case of any failure, the toolkit narrows down to the type of failure based on the various status bits, which are based on the register bank or output port from the hardened custom PCS core or MAC soft logic. The corresponding next-step debugging information is displayed in the Help tab.

Figure 16. Traffic Statistics Tab
The Traffic Statistics tab enables you to configure both the traffic generator and checker in the design example to run in the user-specified traffic mode, and reads traffic statistics. You can also read the traffic statistics in this tab.
Figure 17. Help Tab

The Help tab provides useful next-step debugging information based on the errors or status registers reported from the MAC and PCS status in the MAC and PHY tab.

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