F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 12/04/2023
Public

1.3. Directory Structure

The F-Tile CPRI PHY Intel® FPGA IP core design example file directories contain the following generated files for the design example:
Figure 7. Directory Structure of the Generated Example Design
Table 2.  Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

<design_example_dir>/example_testbench/basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the hardware design example module and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/cpriphy_ftile_wrapper.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/example_testbench/cpriphy_ftile_hw.sv Hardware design example module that instantiates DUT and other testbench components.

Testbench Scripts1

<design_example_dir>/example_testbench/run_vsim.do The Siemens* EDA QuestaSim* , or Questa* Intel® FPGA Edition script to run the testbench.

<design_example_dir>/example_testbench/run_vcs.sh

The Synopsys* VCS* script to run the testbench.
<design_example_dir>/example_testbench/run_vcsmx.sh The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.
<design_example_dir>/example_testbench/run_xcelium.sh The Cadence Xcelium* script to run the testbench.
Table 3.   Hardware Design Example File Descriptions
File Names Descriptions
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.qpf Intel® Quartus® Prime project file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.qsf Intel® Quartus® Prime project settings file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Intel Agilex® 7 device.
<design_example_dir>/hardware_test_design/cpriphy_ftile_hw.v Top-level Verilog HDL design example file.
<design_example_dir>/hardware_test_design/cpriphy_ftile_wrapper.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/hardware_test_design/hwtest_sl/main_script.tcl Main file for accessing System Console.
1 Ignore any other simulator script in the <design_example_dir>/example_testbench/ folder.