F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 12/04/2023
Public

1.6. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel Agilex® 7 device, follow these steps:

  1. Ensure that hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/cpriphy_ftile_hw.qpf.
  3. Edit the .qsf file to assign pins based on your hardware.
  4. Click Processing > Start Compilation.
  5. After successful compilation, a .sof file is available in <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Intel Agilex® 7 device:
    1. Launch the Clock Control application and set new frequencies for the design example:
      • Y1 — 156.25 MHz
      • Y4 — 122.88 MHz, if it is the PMA reference frequency, or else 184.32 MHz
      • Y9A — 153.6 MHz
    2. Click Tools > Programmer > Hardware Setup.
    3. Select a programming device.
    4. Ensure that Mode is set to JTAG.
    5. Select the Intel Agilex® 7 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    6. In the row with your .sof, check the box for the .sof.
    7. Check the box in the Program/Configure column.
    8. Click Start.