F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

2. Design Example Description

The design example demonstrates the basic functionality of the F-Tile CPRI PHY Intel® FPGA IP core. You can generate the design from the Example Design tab in the F-Tile CPRI PHY Intel® FPGA IP parameter editor.

To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. You can choose to generate the design example with or without the RS-FEC feature. The RS-FEC feature is available with 10.1376, 12.1651, and 24.33024 Gbps CPRI line bit rates.
Table 6.  Available Features
CPRI Line Bit Rate (Gbps) RS-FEC Support Reference Clock (MHz) Deterministic Latency Support
1.2288 No 153.6 or 122.88 Yes
2.4576 No 153.6 or 122.88 Yes
3.072 No 153.6 or 122.88 Yes
4.9152 No 153.6 or 122.88 Yes
6.144 No 153.6 or 122.88 Yes
9.8304 No 153.6 or 122.88 Yes
10.1376 With and Without 184.32 or 122.88 Yes
12.1651 With and Without 184.32 or 122.88 Yes
24.33024 With and Without 184.32 or 122.88 Yes

Section Content
Features
Design Example Components
Simulation Design Example
Hardware Design Example
Interface Signals
Design Example Registers

Level Two Title