F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 10/02/2023
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.8. Transceiver Toolkit

Transceiver Toolkit (TTK) via the System Console allows you to validate the transceiver link signal integrity in a system in real time. This feature improves your board bring-up time.
  1. Program the Intel Agilex® 7 device using the .sof file generated in the hardware example design.
  2. To launch the System Console, click Tools > System Debugging Tools > System Console
  3. The available toolkit instances appear in the Toolkit Explorer tab.
  4. Select any of the toolkit instances. A new tab Collection appears that contains the transceiver lane status list.
  5. Turn on the options to display Toolkit Parameters and Channel Parameters.
  6. Review the various GUI features under Channel Parameters.
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