F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

2.2.3. Sources and Probes

The design example uses multiple instances of In-System Sources and Probes IPs (ISSP). These IP instances are mainly used to control the resets, and to capture status. The following tables summarize the different ISSP instances and their functions. For more information, refer to Design Debugging Using In-System Sources and Probes.
Remember: In the following tables, n = number of channels, up to 4.
Table 16.  ISSP Instance 0 (issp_rst)
Port Name Width Description
source 1 + 3*n
Used to control different resets.
  • Bit 0: i_reconfig_reset
  • Bit 1: i_rx_rst_n
  • Bit 2: i_tx_rst_n
  • Bit 3: i_rst_n
probe 1 + 3*n Read back the same signals from source.
Table 17.  ISSP Instance 1 (issp_pll_lock)
Port Name Width Description
source 1 Unused
probe 1 iopll_sclk_locked – PLL lock status from IOPLL that generates sampling_clk.
Table 18.  ISSP Instance 2 (issp_patgen)
Port Name Width Description
source 1*n Unused
probe 1*n checker_pass—asserted when the test is completed without error.
Table 19.  ISSP Instance 3 (issp_dl)
Port Name Width Description
source 1*n restart—resets the pattern generator/checker.
probe 20*n rt_count—captures the value of counter_out from the Round Trip Counter module.
Table 20.  ISSP Instance 4 (issp_status)
Port Name Width Description
source 1*n Unused
probe 20*n
Captures various status signals:
  • Bit 0: o_rx_cdr_lock
  • Bit 1: o_tx_pll_lock
  • Bit 2: o_rx_block_lock
  • Bit 3: o_tx_hip_ready
  • Bit 4: o_rx_pcs_ready
  • Bit 5: o_rx_ready
  • Bit 6: o_tx_ready
  • Bit 7: o_rx_rst_ack_n
  • Bit 8: o_tx_rst_ack_n
  • Bit 9: hyperframe_sync (from pattern checker)
  • Bit 10: rt_cnt_done (from measure_done of Round Trip Counter)
  • Bit 11: error_flag (from pattern checker)
  • Bit 12 to 19: unused
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