F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 683281
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

1.2. Generating the Design

Procedure
Example Design Tab in IP Parameter Editor

To create an Intel® Quartus® Prime Pro Edition project:

  1. In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new project, or File > Open Project to open an existing project. The wizard prompts you to specify a device.
  2. Specify the device family Intel Agilex® 7 (I-series) and select a device that meets all of these requirements:
    • Transceiver tile: F-tile
    • Transceiver speed grade: -1 or -2
    • Core speed grade: -1 or -2 or -3
  3. Click Finish.
Follow these steps to generate the F-Tile CPRI PHY Intel® FPGA IP hardware design example and testbench:
  1. In the IP Catalog, locate and select F-Tile CPRI PHY Intel® FPGA IP. The New IP Variation dialog box appears.
  2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  3. Click OK. The parameter editor appears.
  4. On the IP tab, specify the parameters for your IP core variation.
  5. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  6. On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL. If you select VHDL, you must simulate the testbench with a mixed-language simulator. The device under test in the ex_<datarate> directory is a VHDL model, but the main testbench file is a SystemVerilog file.
  7. Click the Generate Example Design button. The Select Example Design Directory dialog box appears.
  8. If you want to modify the design example directory path or name from the defaults (cpriphy_ftile_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
Figure 2. Analog Parameters Tab
When the CPRI rate is 6.1440G and below, there are extra 3 analog parameters to configure:
  • RXEQ VGA Gain
  • RXEQ High Frequency Boost
  • RXEQ DFE Data Tap1
Figure 3. For CPRI Rates 9.8304G and Above
Figure 4. For CPRI Rates 6.1440G and Below

The default and recommended analog parameters values are shown in the table below:

Table 1.  Default and Recommended Analog Parameter Values
Parameter Value
FGT TXEQ Post Tap 1, 1.0 step size 0
FGT TXEQ Main Tap 1.0 step size 35
FGT TXEQ Pre Tap 1, 1.0 step size 5
FGT TXEQ Pre Tap 2, 1.0 step size 0
FGT RX Onchip Termination RX_ONCHIP_TERMINATION_R_2 (100 ohms)
Enable FGT RX AC Couple ENABLE
Enable FGT VSR mode
  • VSR_MODE_LOW_LOSS (for CPRI rate 24Gbps only)
  • VSR_MODE_DISABLE (shown error if it’s not selected for CPRI rate below 24Gbps)
RXEQ VGA Gain 0 (Required only when CPRI rate is 6.1440Gbps and below)
RXEQ High Frequency Boost 0 (Required only when CPRI rate is 6.1440Gbps and below)
RXEQ DFE Data Tap1 0 (Required only when CPRI rate is 6.1440Gbps and below)

In the Example Design tab, if you select Target Development Kit to be Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit, and you configure analog parameters other than the default and recommended values, you will see warnings to recommend you set to the default values.

Figure 5. Target Development Kit in the Example Design Tab
Figure 6. Warnings
Level Two Title