F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 9/26/2022
Public

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2.2.7. System PLL

The F-tile Reference and System PLL Clocks Intel FPGA IP specifies the frequency of the System PLL and Reference clock in F-tile. You must instantiate this IP in any design that uses F-tile. For more information, refer to Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP.