F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 9/26/2022
Public

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2.2.5. JTAG Host

The JTAG to Avalon Host Bridge Intel FPGA IP sends and receives commands from system console to example design’s Avalon® memory-mapped interface (host of Avalon memory-mapped decoder) via JTAG. In simulation, this block is bypassed, and replaced with a Verilog force statement. The Avalon® memory-mapped interface read and write task simulates the system console operation. For more information, refer to SPI Agent/JTAG to Avalon Host Bridge Cores.