F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 9/26/2022
Public

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2.4. Hardware Design Example

Figure 5. Block Diagram
The F-Tile CPRI PHY Intel® FPGA IP core hardware design example includes the following components:
  • F-Tile CPRI PHY Intel® FPGA IP core.
  • Packet client logic block that generates and receives traffic.
  • Round trip counter.
  • IOPLL to generate the sampling clock for deterministic latency logic inside the IP, and the round trip counter component at testbench.
  • System PLL to generate the system clocks for the IP.
  • Avalon® memory-mapped address decoder to decode reconfiguration address space for CPRI PHY Reconfiguration Interface, PMA Avalon® Memory-Mapped Interface, and Datapath Avalon® Memory-Mapped Interface.
  • Sources and probes for asserting resets and monitoring the clocks and a few status bits.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.