1.3. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0.1 Revision...

Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes

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ID 683245

Date 10/31/2016

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1.3. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v15.0.1 Revision History

Table 5. v15.0.1 June 2015
Description	Impact
Verified in Quartus II software v15.0.1	-
Made the following improvements to the link training (LT) algorithm: Support for manual VGA tuning Added option to skip link partner VOD (main tap) adjustment during LT Added option to enable decision feedback equalization (DFE) at the end of LT General algorithm improvements for stability	-

Table 6. 10GBASE-KR IP Core Register Definition Changes v15.0.1Register definitions added or modified in version 15.0.1 for word address 0x4D0.
Bit	RW	Old Register Name	New Register Name	Description
2	RW	`quick_mode`	Reserved	Reserved
3	RW	`pass_one`	Reserved	Reserved
18	RW	`Ctle_depth`	`VOD Training Enable`	Defines whether or not to skip adjustment of the link partner’s VOD (main tap) during link training. The following values are defined: 1 = Exercise VOD (main tap) adjustment during link training 0 = Skip VOD (main tap) adjustment during link training The default value is 0.
19	RW	`Ctle_depth`	`Bypass DFE`	Defines whether or not Decision Feedback Equalization (DFE) is enabled at the end of link training. The following values are defined: 1 = Bypass continuous adaptive DFE at the end of link training 0 = Enable continuous adaptive DFE at the end of link training The default value for simulation is 1. The default value for hardware is 0.
21:20	RW	`rx_ctle_mode`	`rx_ctle_vga_mode`	Defines the point at which to enable the RX CTLE in the adaptation algorithm. The following values are defined: 00 = never, the RX CTLE isn’t enabled or adjusted 01 = trigger CTLE/VGA before starting TX-EQ 10 = trigger CTLE/VGA after finishing TX-EQ 11 = trigger CTLE/VGA, both before starting, and after finishing TX-EQ The default value is 00. Note: These bits are only effective when 0x4D0[22] is set to 0.
22	RW	Reserved	`adp_ctle_vga_mode`	Defines whether or not CTLE/VGA adaptation is in adaptive or manual mode. The following values are defined: 1 = Manual CTLE/VGA mode. Link training algorithm sets fixed CTLE and VGA values as specified in bits 0x4D0[28:24] and 0x4D0[31:29], respectively. 0 = adaptive CTLE mode. Bits in 0x4D0[21:20] are effective only when this bit is set to 0. The default value is 1.
28:24	RW	Reserved	`Manual CTLE`	Defines the CTLE value used by the link training algorithm when in manual CTLE mode. These bits are only effective when 0x4D0[22] is set to 1. The default value is 1.
31:29	RW	`max_post_step[2:0]`	`Manual VGA`	Defines the VGA value used by the link training algorithm when in manual VGA mode. These bits are only effective when 0x4D0[22] is set to 1. The default value is 4.