1.1. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v16.0 Revision...

Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes

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ID 683245

Date 10/31/2016

Version current

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Visible to Intel only — GUID: joc1461701367477

Ixiasoft

1.1. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v16.0 Revision History

Table 1. v16.0 May 2016
Description	Impact
Verified in Quartus Prime software v16.0	-
Made the following changes: Changed descriptions in the register definitions.	-

Table 2. 10GBASE-KR IP Core Register Definition Changes v16.0Register definitions added or modified in version 16.0 for word address 0x4D0.
Bit	RW	Old Register Name	New Register Name	Description
1	RW	`dis_max_wait_tmr`	—	When set to 1, disables the LT `max_wait_timer`. Used for characterization mode when setting much longer BER timer values. The default value is 0.
14:12	RW	`equal_cnt [2:0]`	—	Adds hysteresis to the error count to avoid local minimums. The following values are defined: 000 = 0 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 The default value is 101.
21:20	RW	`rx_ctle_vga_mode`	`dfe_freeze_mode`	Defines the behavior of DFE taps at the end of link training 00 = do not freeze any DFE taps 01 = Freeze all DFE taps 10 = reserved 11 = reserved The default value is 01. Note: These bits will be effective only when bit [19] is set to 0.
22	RW	`adp_ctle_vga_mode`	—	Defines whether or not CTLE/VGA adaptation is in adaptive or manual mode. The following values are defined: 0 = CTLE sweep before start of TX-EQ during link training. 1 = manual CTLE mode. Link training algorithm sets fixed CTLE value, as specified in bits [28:24]. The default value is 1 for simulation. The default value is 0 for hardware.
31:29	RW	`Manual VGA`	—	Defines the VGA value used by the link training algorithm when in manual VGA mode. These bits are only effective when 0x4D0[22] is set to 1. The default value is 4 for simulation. The default value is 7 for hardware.
22	RW	`adp_ctle_vga_mode`	—	Defines whether or not CTLE/VGA adaptation is in adaptive or manual mode. The following values are defined: 0 = CTLE sweep before start of TX-EQ during link training. 1 = manual CTLE mode. Link training algorithm sets fixed CTLE value, as specified in bits [28:24]. The default value is 1 for simulation. The default value is 0 for hardware.