Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core Release Notes

ID 683245
Date 10/31/2016
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1.6. Arria 10 1G/10GbE and 10GBASE-KR PHY IP Core v14.0 Revision History

Table 9.  v14.0 August 2014
Description Impact
Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. -
Removed the following parameters from the Link Training tab:
  • Enable daisy chain mode.
  • Enable microprocessor interface.
-
Changed the default values of the following PMA parameters under the Link Training tab:
  • VMAXRULE
  • VMINRULE
  • VODMINRULE
  • VPOSTRULE
  • VPRERULE
  • PREMAINVAL
  • INITMAINVAL
  • INITPOSTVAL
  • INITPREVAL
-
Changed Avalon Memory-Mapped (AVMM) clock frequency from 125 MHz to 161 MHz to support NIOS II. The AVMM slave interface provides access to the IP core registers. -
IEEE 1588 Precision Time Protocols are not supported in backplane applications. -
Link Training takes more time in simulation as NIOS command processing is slower. -