Quartus® Prime Pro Edition User Guide: Design Compilation

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Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Using the Node Finder 1.3. Design Analysis & Elaboration 1.4. Design Synthesis 1.5. Design Place and Route 1.6. Incremental Optimization Flow 1.7. Fast Forward Compilation Flow 1.8. Full Compilation Flow 1.9. HSSI Dual Simplex IP Generation Flow 1.10. Exporting Compilation Results 1.11. Integrating Other EDA Tools 1.12. Compiler Optimization Techniques 1.13. Compilation Monitoring Mode 1.14. Synthesis Language Support 1.15. Synthesis Settings Reference 1.16. Fitter Settings Reference 1.17. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Using the Compilation Dashboard 1.1.4. Design Netlist Infrastructure
1.1.4. Design Netlist Infrastructure x
1.1.4.1. DNI Netlist Five-Box Data Model
1.3. Design Analysis & Elaboration x
1.3.1. Using the RTL Analyzer 1.3.2. Use Case Examples
1.3.1. Using the RTL Analyzer x
1.3.1.1. Sweep Hints Viewer 1.3.1.2. Object Set Console 1.3.1.3. Module Interfaces 1.3.1.4. Bundled Instances 1.3.1.5. Auto-hide Unconnected Pins 1.3.1.6. Filtering Ports and Nets 1.3.1.7. Expand Connections
1.3.2. Use Case Examples x
1.3.2.1. Scripting Routine Tasks Using Tcl Commands 1.3.2.2. Traversing the Design Netlist Using Tcl Commands
1.4. Design Synthesis x
1.4.1. Preparing for Design Synthesis 1.4.2. Running Synthesis 1.4.3. Using Synopsys* Design Constraint (SDC) on RTL Files 1.4.4. Post-Synthesis Static Timing Analysis (STA) 1.4.5. Viewing Synthesis Reports 1.4.6. Viewing Synthesis Dynamic Report
1.4.2. Running Synthesis x
1.4.2.1. Preserving Registers During Synthesis 1.4.2.2. Preserving Signals for Monitoring and Debugging
1.4.3. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.4.3.1. Registering the SDC-on-RTL SDC File 1.4.3.2. Applying the SDC-on-RTL Constraints 1.4.3.3. Inspecting SDC-on-RTL Constraints 1.4.3.4. Creating Constraints in SDC-on-RTL SDC Files 1.4.3.5. Using Entity-Based SDC-on-RTL Constraints 1.4.3.6. Types of SDC Files Used in the Quartus® Prime Software 1.4.3.7. Example: Using SDC-on-RTL Features
1.5. Design Place and Route x
1.5.1. Running the Fitter 1.5.2. Viewing Fitter Reports
1.5.1. Running the Fitter x
1.5.1.1. Fitter Commands 1.5.1.2. Disabling or Enabling Physical Synthesis Optimization
1.5.2. Viewing Fitter Reports x
1.5.2.1. Plan Stage Reports 1.5.2.2. Place Stage Reports 1.5.2.3. Route Stage Reports 1.5.2.4. Retime Stage Reports 1.5.2.5. Finalize Stage Reports
1.5.2.2. Place Stage Reports x
1.5.2.2.1. Global Signal Visualization Report
1.5.2.3. Route Stage Reports x
1.5.2.3.1. Global Router Congestion Hotspot Summary Report 1.5.2.3.2. Global Router Wire Utilization Map Report
1.6. Incremental Optimization Flow x
1.6.1. Concurrent Analysis During Synthesis or Fitting 1.6.2. Analyzing Compiler Snapshots 1.6.3. Validating Periphery (I/O) after the Plan Stage
1.6.2. Analyzing Compiler Snapshots x
1.6.2.1. Running Snapshot Viewer
1.6.2.1. Running Snapshot Viewer x
1.6.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.6.2.1.2. Analyzing Clocking with Snapshot Viewer 1.6.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.6.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.6.2.1.5. Analyzing Congestion with Snapshot Viewer
1.7. Fast Forward Compilation Flow x
1.7.1. Step 1: Run Register Retiming 1.7.2. Step 2: Review Retiming Results 1.7.3. Step 3: Run Fast Forward Compile 1.7.4. Step 4: Review Fast Forward Results 1.7.5. Step 5: Implement Fast Forward Recommendations 1.7.6. Retiming Restrictions and Workarounds
1.7.2. Step 2: Review Retiming Results x
1.7.2.1. Locate Critical Chains
1.7.3. Step 3: Run Fast Forward Compile x
1.7.3.1. Fast Forward Compile By Hierarchy 1.7.3.2. HyperFlex Settings
1.7.4. Step 4: Review Fast Forward Results x
1.7.4.1. Clock Fmax Summary Report 1.7.4.2. Fast Forward Details Report
1.8. Full Compilation Flow x
1.8.1. Full Compilation Flow with Temporary Optimization Mode
1.10. Exporting Compilation Results x
1.10.1. Exporting a Version-Compatible Compilation Database 1.10.2. Importing a Version-Compatible Compilation Database 1.10.3. Creating a Design Partition 1.10.4. Exporting a Design Partition 1.10.5. Reusing a Design Partition 1.10.6. Viewing Quartus Database File Information 1.10.7. Clearing Compilation Results
1.10.6. Viewing Quartus Database File Information x
1.10.6.1. QDB File Attribute Types
1.11. Integrating Other EDA Tools x
1.11.1. Generating a VQM Netlist for other EDA Tools
1.12. Compiler Optimization Techniques x
1.12.1. Compiler Optimization Modes 1.12.2. Precompiled Component (PCC) Generation Stage 1.12.3. Compilation on a Compute Farm 1.12.4. Allow Register Retiming 1.12.5. Automatic Gated Clock Conversion 1.12.6. Enable Intermediate Fitter Snapshots 1.12.7. Fast Preserve Option 1.12.8. Fractal Synthesis Optimization
1.12.8. Fractal Synthesis Optimization x
1.12.8.1. Enabling or Disabling Fractal Synthesis
1.14. Synthesis Language Support x
1.14.1. Verilog and SystemVerilog Synthesis Support 1.14.2. VHDL Synthesis Support
1.14.1. Verilog and SystemVerilog Synthesis Support x
1.14.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.14.1.2. Design Libraries 1.14.1.3. Verilog HDL Configuration 1.14.1.4. Initial Constructs and Memory System Tasks 1.14.1.5. Verilog HDL Macros
1.14.1.3. Verilog HDL Configuration x
1.14.1.3.1. Hierarchical Design Configurations
1.14.2. VHDL Synthesis Support x
1.14.2.1. VHDL Input Settings (Settings Dialog Box) 1.14.2.2. VHDL Standard Libraries and Packages 1.14.2.3. VHDL wait Constructs 1.14.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.15. Synthesis Settings Reference x
1.15.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Running the ECO Compilation Flow 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
2.3.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.2. Use Appropriate Coding Style to Reduce Synthesis Time
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion 2.5.2. Changing Fitter Aggressive Routability Optimization Settings
2.5.1. Identifying Routing Congestion x
2.5.1.1. Identifying Congestion with the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map 2.5.1.2. Identifying Routing Congestion with the Chip Planner
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.2. Using the Node Finder

Use the Node Finder tool to search for objects in the design databases based on specific search criteria. The Node Finder serves as a central tool for exploring nodes throughout the design cycle. It provides a list of matching nodes, that you can cross-probe with other tools like the RTL Analyzer and Timing Analyzer. Searches can be initiated after completing at least the Analysis and Elaboration compilation stage from the Quartus compilation dashboard.

To launch the Node Finder, on the Quartus® Prime software menu, click View > Node Finder.

The Named field serves as the starting point for initiating a search. It accepts partial or full-text characters and standard wildcard characters (" * " and " ? "). When you click Search, the Node Finder searches all node names matching the specified text. Your search strings are saved, so you can access previously searched strings using the drop-down. The Node Finder provides additional search options (described in the section below) to refine your search.

In the following example, the Node Finder has found all user-entered names in your design files:

This example uses a * wildcard to show all user-entered names in the design. To avoid reviewing a large list of nodes when you look for a particular node or nodes in your design, use a more specific wildcard, or search options.

The attributes of the Node Finder vary depending on the database being accessed. By default, the Named field is case-sensitive when retrieving elements from the design netlist database. However, you can adjust this setting through the option provided when you click the Options button. In contrast, elements retrieved from the timing netlist database are always case-insensitive.

Node Finder Search Options

Use the Show More Search Options button in the Node Finder to show or hide the Options panel where you can apply filters and refine your search. The button is to the right of Search button as shown highlighted in the following figure:

Figure 4. Show More Search Options Button


Search options available in the Node Finder vary based on the filter you select in the Filter drop-down list. For descriptions of the filters, refer to Node Finder Search Filters . You can also access additional options to customize the filter by clicking Options or Customize, depending on which button is displayed. The additional options available depend on the selected filter. Some options are enabled, disabled, or grayed out by default.

Figure 5. Filter Options


Table 5.  Node Finder Search Options
Node Finder Search Options Description
Customize

(Timing netlist searches)
  • Filter: Provides preset filter settings and facilitates the creation of custom filters based on existing ones.
  • View: Allows selection between retrieving data from current project settings or from the last compilation.
  • Use Netlist: Allows you to select the compiler netlist to use for searching in the Node Finder from the following options:
    • Pre-Synthesis: The netlist is written out after the Analysis and Elaboration step of Synthesis and before Logic Synthesis
    • Post-Synthesis: The netlist is written out at the end of Synthesis
    • Post-Fitting: The netlist is written out at the end of Fitter.
  • Show Names Matching: Determines the types of objects that will match the search.
  • Creator: Filters between netlist objects that are user entered or compiler-generated:
    • User-entered objects are those whose names are specified by the user in their design source files.
    • Compiler-generated objects are netlist objects instantiated by the compiler during the compilation and optimization process.
Options

(Design netlist searches)
  • Case-insensitivity: Allows searching case-insensitive node names. By default, the search is case-sensitive. With this option enabled, the search returns the same result irrespective of whether you use lowercase or uppercase search strings.
  • Object Type: Specifies the object type to search for. You can choose between instance, instance_bus, instance_port, port, port_bus, net, and net_bus.
  • Properties: Allows adding or removing object properties, such as object name, name of an object's parent, number of ports, source file or line number in the source, and so on. You can type the property values (integer or string) manually.
Table 6.  Node Finder Search Additional Options
Node Finder Search Options Description
Look in

Refines your search hierarchy path.

When you select Timing Netlist filter, use the Browse button to choose the desired search hierarchy level. Clicking the Browse opens the Select Hierarchy Level dialog box.

For a Design Netlist filter, select the desired hierarchy level in the hierarchy tree located below the Look In field.

Include subentities

Enable this option to include names that match the specified pattern in deeper hierarchies recursively during a search.

Enabling this option can be helpful when searching for names that match a specific pattern throughout the entire design hierarchy.

Alternatively, if you are looking for a specific name within a module that contains other instantiations, specify the hierarchy level and disable this option to avoid a recursive search and unnecessary matches in deeper hierarchies.

Hierarchy view

A hierarchal view of search results is available for filters that target the timing netlist. This view can help you focus on specific instances in your design.

Use this option to switch between a list format and a hierarchical view of your results.

Node Finder Search Filters

The following search filters are available in the Node Finder:

Table 7.  Node Finder Filters and Search Mode
Filter Name Description
Design Entry (all names) Finds all user-entered names in the search hierarchy path.
Pins: assigned Finds all assigned pins in the search hierarchy path.
Pins: unassigned Finds all unassigned pins in the search hierarchy path.
Pins: input Finds all input pins in the search hierarchy path.
Pins: output Finds all output pins in the search hierarchy path.
Pins: bidirectional Finds all bidirectional pins in the search hierarchy path.
Pins: virtual Finds all I/O elements mapped to logic elements with a virtual pin logic option assignment.
Pins: all Finds all pins in the search hierarchy path.
Pins: all & Registers: post-fitting Finds all pins and registers that persist after physical synthesis and fitting within the search hierarchy path.
Note: This filter is a combination of the Pins: all and Registers: post-fitting filters.
Ports: partition Finds all user-entered and compiler-generated partition ports within the post-fit netlist and search hierarchy path.
Entity instance: pre-synthesis Finds all entity instances within the pre-synthesis netlist and search hierarchy path.
Registers: pre-synthesis Finds all user-entered register names contained in the design after Analysis & Elaboration, but before physical synthesis performs any synthesis optimizations.
Registers: post-fitting Finds all user-entered registers in the search hierarchy path that survived physical synthesis and fitting.
Post-synthesis Finds all user-entered and synthesis-generated nodes contained in the design after design elaboration and physical synthesis.
Post-synthesis: preserved for debug Finds all internal device nodes that you have designated with preserve for debug in the post-synthesis netlist.
Post-Compilation Finds all user-centered and compiler-generated names that persist post-fit and do not have location assignments.
Signal Tap: pre-synthesis Finds all internal device nodes in the pre-synthesis netlist that are preserved for analysis by the Signal Tap Logic Analyzer.
Signal Tap: post-fitting Finds all internal device nodes in the post-fit netlist that are preserved for analysis by the Signal Tap Logic Analyzer.
Signal Tap: post-fitting user defined Finds all user defined internal device nodes in the post-fit netlist that are preserved for analysis by the Signal Tap Logic Analyzer.
Signal Tap: pre-synthesis preserved for debug Finds all internal device nodes in the pre-synthesis netlist that are preserved for analysis by the Signal Tap Logic Analyzer.
Signal Tap: post-fitting preserved for debug Finds all internal device nodes in the post-fit netlist that are preserved for analysis by the Signal Tap Logic Analyzer.

In the following example, we want to verify that three arrays of registers named Sum1Stg1, Sum2Stg1, and Sum3Stg each contain six individual registers, and that these registers are included in the design after physical synthesis.

The Node Finder is configured to retrieve nodes that match the pattern " Sum*Stg1* ", with the " * " character serving as a wildcard character. This pattern enables the Node Finder to retrieve all the register arrays at once, including each individual register from Sum1Stg1, Sum2Stg1, and Sum3Stg1. The Post-synthesis filter targets synthesis-generated nodes contained in the design after design elaboration and physical synthesis.

Additionally, by specifying a particular hierarchy level through the Look In field, and using the Include subentities option, the Node Finder can save time by constraining the search to specific hierarchy levels.

The Hierarchy view provides a structured view of the results, making them easier to navigate.



The results of Node Finder search lets us see that some registers are missing in the Sum2Stg1 array.

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