Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 3/28/2022

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Document Table of Contents

2. Design Compilation

The Intel® Quartus® Prime Compiler synthesizes, places, and routes your design before generating device programming files. The Compiler supports a variety of high-level, HDL, and schematic design entry methods. The modules of the Compiler include IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and Assembler.
Compilation Dashboard

The Intel® Quartus® Prime Pro Edition version of the Compiler supports these advanced features:

  • Supports Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ devices.
  • Incremental Fitter optimization—analyze and optimize after each Fitter stage to maximize performance and shorten total compilation time.
  • Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation for the highest performance in Intel® Stratix® 10 and Intel® Agilex™ devices.
  • Partial Reconfiguration—dynamic reconfiguration of a portion of the FPGA, while the remaining FPGA continues to function.
  • Block-Based Design Flows—preservation and reuse of design blocks.