Nios II Embedded Design Suite Release Notes

ID 683228
Date 6/17/2015
Document Table of Contents

1.3.2. New Embedded IPs for 14.1

The list of new IP includes:

  • HPS Ethernet converter IPs - These allow you to assign the HPS Ethernet I/O pins to FPGA I/O pins and convert them from GMII format to RGMII or SGMII.
    Note: This is very helpful if you are pin limited by the HPS I/O.
  • New device family-specific IP cores:
    • Arria 10 - TPIU trace IP. Trace is the ultimate tool in runtime software debug, much like Signaltap is for FPGA development. This IP enables developers to export the ARM® Cortex™-A9 trace debug signals to external pins so that trace debug modules like Lauterbach® or ARM Dstream, can be connected to the A10 SoC Cortex-A9.
    • Max 10 - New IPs that deliver Qsys compatible interfaces to the Max10 ADCs and user flash. These new IPs are used in the Max10 example designs.

The 14.1 release has new example designs that demonstrate:

  • Max 10 sleep mode, for low power applications
  • Analog I/O for developers that want to use the integrated ADCs
  • Dual configuration capability from the Max 10 on-chip configuration flash memory

The Cyclone® V and ArriaV SoC golden system reference designs (GSRDs) have also been updated to support the 14.1 ACDS and SoC EDS releases, this means that they will automatically include the SoC software fixes in 14.1 like the PLL workaround in the preloader.