O-RAN Intel® FPGA IP Design Example User Guide

Download PDF
ID 683218
Date 8/15/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP Design Example 2. Getting Started with the O-RAN Intel® FPGA IP Design Example 3. O-RAN Intel® FPGA IP Design Example Functional Description 4. O-RAN IP Design Example User Guide Archives 5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
2. Getting Started with the O-RAN Intel® FPGA IP Design Example x
2.1. Generating the O-RAN IP Design Example 2.2. Simulating the O-RAN IP Design Example 2.3. Operating the O-RAN IP Design Example
2.1. Generating the O-RAN IP Design Example x
2.1.1. O-RAN IP Design Example Parameters
2.2. Simulating the O-RAN IP Design Example x
2.2.1. Simulating the O-RAN Design Example for Intel Agilex® 7 F-Tile Devices 2.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP 2.2.3. O-RAN IP Design Example Testbench
2.3. Operating the O-RAN IP Design Example x
2.3.1. Generating and Downloading the Programming .elf File
1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide

2.3.1. Generating and Downloading the Programming .elf File

Generate and download the .elf file for the O-RAN IP design example to the development board. For Intel® Stratix® 10 designs and Intel Agilex® 7 E-tile only.
  1. Change the directory to <design_example_dir>/synthesis/quartus.
  2. In the Intel® Quartus® Prime Pro Edition software, click Open Project and open <design_example_dir>/synthesis/quartus/oran_ed.qpf.
  3. Select Tools > Nios II Software Build Tools for Eclipse.
    The Workspace Launcher window prompt appears.
  4. In the workspace specify the path as <design_example_dir>/synthesis/quartus to store your Eclipse project. A new Nios II - Eclipse window appears.
  5. In the Nios II - Eclipse window, right-click under Project Explorer tab, and select New > Nios II Board Support Package.
    Figure 14. Project Explorer Window
  6. In the Nios II Board Support Package window:
    1. In the Project name parameter, specify your desired project name.
    2. In the SOPC Information File name parameter, browse to the location of <design_example_dir>/synthesis/ip_components/nios_system/nios_system.sopcinfo file.
    3. Click Finish.
    Figure 15. Nios II Board Support Package Window
    The newly created project appears under Project Explorer tab in Nios II - Eclipse window.
  7. Right-click under Project Explorer tab and select Nios II > Nios II Command Shell.
    Figure 16. Project Explorer - Nios II Command Shell
  8. In the Nios® II Command Shell, type the three following commands:
    nios2-bsp hal bsp <design_example_dir>/synthesis/ip_components/nios_system/nios_system.sopcinfo
    nios2-app-generate-makefile --app-dir app --bsp-dir bsp --elf-name nios_system.elf --src-dir <design_example_dir>/synthesis/compilation/ed_fw
    make --directory=app
  9. Type the following command in the Nios® II Command Shell to download the .elf software application to the board:
    nios2-download -g -r -c 1 -d 2 --accept-bad-sysid app/nios_system.elf
Level Two Title