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1. About the O-RAN Intel® FPGA IP Design Example
2. Getting Started with the O-RAN Intel® FPGA IP Design Example
3. O-RAN Intel® FPGA IP Design Example Functional Description
4. O-RAN IP Design Example User Guide Archives
5. Document Revision History for the O-RAN Intel® FPGA IP Design Example User Guide
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2.2.3. O-RAN IP Design Example Testbench
The generated simulation testbench is dynamic and has the same configuration as the IP.
Figure 8. Testbench Block Diagram
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