1.1. Introduction
1.2. Bare Metal Overview
1.3. Prerequisites for the Bare Metal Development Environment
1.4. Bare Metal Compiler
1.5. Bare Metal Development Flow
1.6. Using DS-5 AE to Create and Manage Bare Metal Projects
1.7. Importing, Building and Debugging in a Make-Based Example
1.8. DS-5 ARM HWLIBs Project Derived from Make-Based Project
1.9. Minimal Preloader
1.10. Appendix: Troubleshooting
1.9. Minimal Preloader
The Minimal Preloader (MPL) is an alternative for the General Public License (GPL) Preloader. It uses the BSD license and may be freely distributed and modified according to the terms of that license. The MPL supports a subset of features supported by Altera's GPL Preloader.
The MPL initializes the PLLs, reset signals, configures IOCSR and pin MUXing, and performs other configuration-based on the preloader generator file settings. It can also load the FPGA from a boot source, if desired. It then reads a secondary image from a boot source into RAM and hands control to that image.
This version of MPL supports booting from QSPI, SD/MMC and FPGA.
Note: NAND boot is not supported.
The MPL uses Altera HWLib drivers for most of its functionality. It also uses Altera HWLib SoCAL folders for the memory map definitions and basic read and write commands.
The MPL supports both the ARMCC and GNU GCC compilers. The MPL supports both Cyclone V SoC and Arria V SoC devices.
Note: Arria 10 SoC devices are not supported.
The example project in the following section is for Cyclone V SoC. Please modify the example as needed to select appropriate file names.