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1.3. Generating the Design
Configure the SDI II Intel® FPGA IP parameter editor in the Intel® Quartus® Prime software to generate the design examples.
Figure 3. Generating the Design Flow
- Create a project targeting the Intel® Arria® 10 device family and select the desired device.
- In the IP Catalog, locate and double-click SDI II Intel® FPGA IP. The New IP Variant or New IP Variation window appears.
- Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip /<your_ip>.qsys.
- Click OK. The parameter editor appears.
- On the IP tab, select your desired IP settings. The generated design example is based on your settings.
- On the Design Example tab, select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
You must select at least one of these options to generate the design example files.
- For Generate File Format, select Verilog or VHDL.
- For Select Board, select the relevant FPGA development kit. You may change the target device using the Change Target Device parameter if your board revision does not match the grade of the default targeted device.
- For Select Daughter Card, select Nextera VIDIO 12G-SDI FMC card or Terasic FMC card to pair with an Intel FPGA development kit. If you choose not to use a development kit or use your own custom kit, this parameter will be grayed out, and the generated design will use the on-board SMB pin as a serial data pin.
- Click Generate Example Design.
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