SDI II Intel® Arria 10 FPGA IP Design Example User Guide

ID 683209
Date 3/28/2022

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1.5. Compiling and Testing the Design

To compile and run a demonstration test on the hardware design example, follow these steps:
  1. Ensure that the hardware design example generation is complete.
  2. Open quartus/sdi_ii_a10_demo.qpf.
  3. Click Processing > Start Compilation.
  4. If you set the Rx core clock (rx_coreclk) Frequency parameter to 297.0/296.70 MHz, set the frequency for CLK1 in the Si5338 (U14) tab of the Clock Control GUI to 297 MHz.
  5. If you enable the Dynamic Tx clock switching feature in the Design Example parameter editor, set the frequency for CLK2 or CLK3 in the Si5338 (U14) tab of the Clock Control GUI.
    • For HD/3G-SDI single-rate and triple-rate designs, set CLK3 to 148.3516 MHz.
    • For multi-rate designs, set CLK2 to 296.7033 MHz.
  6. After successful compilation, the Intel® Quartus® Prime software generates a .sof file in your specified directory.
  7. Configure the selected Intel® Arria® 10 device on the development board using the generated .sof file (Tools > Programmer ).
  8. For serial loopback designs, open the System Console to control the internal video pattern generator. Click Tools > System Debugging Tools > System Console.
    Note: Close the Clock Control GUI and the Programmer window before you open the System Console.
  9. After the initialization, type source ../hwtest/tpg_ctrl.tcl in the System Console to open the pattern generator control user interface. Select your desired video format.

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