AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

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ID 683197
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface x
1.1. Introduction 1.2. Requirements 1.3. Downloading and Installing the Reference Design 1.4. Walkthrough 1.5. Document Revision History for RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.2. Requirements x
1.2.1. Software Requirements 1.2.2. Hardware Requirements 1.2.3. Features of the RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.4. Walkthrough x
1.4.1. Hardware Setup 1.4.2. Programming the FPGA 1.4.3. Running the Design 1.4.4. System Console User Interface Commands 1.4.5. Register Address Map
1.4.2. Programming the FPGA x
1.4.2.1. Using a Nios® II Command Shell 1.4.2.2. Using the Programmer
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface

1.4.4. System Console User Interface Commands

Please refer to the below table for the description of the user interface commands:
Table 3.  System Console User Interface Commands
Command Description
r Toggles the RapidIO II IP reset input signal. Resets the Rapid IO II IP core.
rc Toggles the Transceiver Reset Controller reset input signal. Resets the transceiver PCS and PMA.
ds Disables the scrambler and descrambler in the RapidIO II IP core. Use for diagnosis purpose.
es Enables the scrambler and descrambler.
link Reports the status of the RapidIO link.
cfig Enables the Input and Output ports and disables Destination ID checking, randomly accepting all incoming request packets.
start Programs the number of packets to be transmitted to 0xFFFFFFFF and enables the traffic generator. The generator stops after transmitting 0xFFFFFFFF packets.
stop Stops the traffic generator.
send Takes an integer value representing the number of packets to send. For an example, send 100: Generates 100 packets.
cstats Clear statistics counters.
stats Report statistics counters.
reinit Toggles the PORT_DIS bit of register 0x15C causing an internal re-initialization of the RapidIO II IP. Helps in diagnosing link up issues.
f4x Forces the RapidIO II IP into 4x mode.
f2x Forces the RapidIO II IP into 2x mode.
f1x Forces the RapidIO II IP into 1x mode.
lps Loop back set, programs the transceivers into serial loopback, TX to RX at the PMA output buffers.
lpc Clears loop back.
lpt Clears the transceiver loopback and then sets it again, toggling serial loopback in the PMA output buffers.
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