AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface

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ID 683197
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface x
1.1. Introduction 1.2. Requirements 1.3. Downloading and Installing the Reference Design 1.4. Walkthrough 1.5. Document Revision History for RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.2. Requirements x
1.2.1. Software Requirements 1.2.2. Hardware Requirements 1.2.3. Features of the RapidIO II Reference Design for the Avalon® -ST Pass-Through Interface
1.4. Walkthrough x
1.4.1. Hardware Setup 1.4.2. Programming the FPGA 1.4.3. Running the Design 1.4.4. System Console User Interface Commands 1.4.5. Register Address Map
1.4.2. Programming the FPGA x
1.4.2.1. Using a Nios® II Command Shell 1.4.2.2. Using the Programmer
1. RapidIO II Reference Design for Avalon® -ST Pass-Through Interface

1.4.1. Hardware Setup

Perform the following steps to setup the hardware for the reference design:

  1. Insert the FMC Loopback Card to the FMC port on the Intel® Stratix® 10 GX FPGA development board.
  2. Connect the Intel® FPGA Download Cable II to the Intel® Stratix® 10 GX FPGA development board and to your host computer.
  3. Connect the power adapter shipped with the development board to the power supply jack.
  4. Set the DIP switches of the Intel® Stratix® 10 GX FPGA development board as specified below:
    Table 2.  DIP Switch Control Settings
    DIP Switch Schematic Signal Name Setting
    SW8 1 I2C_SDA ON
    2 I2C_SCL ON
    3 FPGA_PWRGD OFF
    SW4 1 RZQ_B2M OFF
    2 SI516_FS OFF
    SW3 1 CLK0_OEn OFF
    2 CLK0_RSTn OFF
    3 FACTORY_LOAD OFF
    SW2 1 PCIE_PRSNT2n_x16 OFF
    2 PCIE_PRSNT2n_x8 OFF
    3 PCIE_PRSNT2n_x4 OFF
    4 PCIE_PRSNT2n_x1 OFF
    SW6 1 S10JTAG_BYPASSn OFF
    2 M5JTAG_BYPASSn OFF
    3 FAJTAG_BYPASSn ON
    SW1 1 MSEL2 ON
    2 MSEL1 ON
    Figure 4. DIP Switches Bottom View
    Figure 5. DIP Switches Top View
  5. Turn on the power for the Intel® Stratix® 10 GX FPGA development board.
    The hardware systems is now ready for programming.
    Figure 6. Reference Design Hardware Setup
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