2.8.1. Link Consistency
2.8.2. Data Rate
2.8.3. Reference Clock Frequency
2.8.4. Port Type
2.8.5. Self Synchronized Link Up
2.8.6. Scramble
2.8.7. Broadcast Mode
2.8.8. Lane Polarity and Order Reversal
2.8.9. Data Type
2.8.10. Packet Type
2.8.11. Flow Control Operation
2.8.12. Transmit/Receive FIFO Buffers
2.8.13. Data Integrity Protection: CRC
2.8.14. Transceiver Configuration
2.8.15. Error Handling
2.8.16. Optimizing the Implementation
1. SerialLite II IP Core Overview
Updated for: |
---|
Intel® Quartus® Prime Design Suite 16.1 |
IP Version 16.1 |
The SerialLite II IP core is a lightweight protocol suitable for packet and streaming data in chip-to-chip, board-to-board, and backplane applications.
The SerialLite II protocol offers low gate count and minimum data transfer latency. It provides reliable, high-speed transfers of packets between devices over serial links. The protocol defines packet encapsulation at the link layer and data encoding at the physical layer, and integrates transparently with existing networks without software support.
Information | Description |
---|---|
Version | 16.1 |
Release Date | October 2016 |
Ordering Code | IP-SLITE2 |
Device Family Support |
Intel® Arria® 10, Arria® V, Arria® II GX, Cyclone® V, Stratix® V, and Stratix® IV device families.
Note: Intel® Arria® 10 devices are indirectly supported by the SerialLite II IP core version 15.0 and later. If your design needs to implement SerialLite II interface in Intel® Arria® 10 devices, contact your local Intel representative or file a Service Request (SR) to obtain a design example, a guideline document, and a special license to enable the Intel® Quartus® Prime software to generate the FPGA configuration file (.sof) for the Intel® Arria® 10 devices.
|
Intel verifies that the current version of the Intel® Quartus® Prime software compiles the previous version of each IP core. The IP Core Release Notes and Errata report any exceptions to this verification. Intel does not verify compilation with IP core versions older than one release.
Features | Description |
---|---|
Physical layer features |
|
Link layer features |
|
Related Information
1 For Intel® Arria® 10 devices, the IP core supports higher than 6.375 Gbps per lane.