SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

1.2. Performance and Resource Utilization

The performance and resource utilization table lists the resources and internal core speeds for a selection of variations using a 1,024-byte FIFO buffer.
Table 3.  Performance for Stratix IV DevicesThese results were obtained using the Quartus Prime software version 16.0 for the Stratix IV device (EP4SGX70HF35C2).

Lane Packet Type Transfer Size CRC ROE FC Through-put at Mbps RX Buffer Size (Data) RX Buffer Size (Prio) Combinational ALUT Memory 9K Memory ALUT Logic Register
1 Data 1 0 0 0 1250 – – 841 10 18 856
1 Data 2 0 0 0 3125 – – 847 11 0 820
1 Data 4 0 0 0 6375 – – 935 21 20 959
4 Data 1 0 0 0 1250 – – 1399 21 56 1291
4 Data 2 0 0 0 3125 – – 1636 31 112 1507
4 Data 4 0 0 0 6375 – – 2184 50 0 1748
16 Data 2 0 0 0 3125 – – 4416 87 308 3656
16 Data 4 0 0 0 6375 – – 6685 181 0 5066
1 Data 1 32 0 1 1250 1024 – 1135 11 35 1265
1 Data 2 32 0 1 3125 1024 – 1189 12 16 1206
1 Data 4 32 0 1 6375 2048 – 1413 22 36 1357
4 Data 1 32 0 1 1250 2048 – 1814 22 72 1675
4 Data 2 32 0 1 3125 4096 – 2380 32 128 1995
4 Data 4 32 0 1 6375 8192 – 3402 51 16 2326
1 Priority 2 16 1 1 3125 – 1024 1519 21 16 1396
1 Priority 4 16 1 1 6375 – 2048 1745 32 36 1541
4 Priority 2 16 1 1 3125 – 4096 2687 51 128 2165
4 Priority 4 16 1 1 6375 – 8192 3661 71 488 3626
Table 4.  Fmax for Stratix IV DevicesThe performance results were obtained using these frequencies at 900 mV 85°C Corner.

Lane Packet Type Transfer Size Fmax (txrdp_clk)

MHz

 Fmax (rxrdp_clk)

MHz

 Fmax (txhpp_clk)

MHz

 Fmax (rxhpp_clk)

MHz
1 Data 1 252.78 261.3 – –
1 Data 2 294.38 302.57 – –
1 Data 4 292.06 298.06 – –
4 Data 1 287.77 286.62 – –
4 Data 2 285.47 299.94 – –
4 Data 4 325.31 292.91 – –
16 Data 2 312.99 285.8 – –
16 Data 4 260.35 247.52 – –
1 Data 1 258.67 274.73 – –
1 Data 2 281.61 256.02 – –
1 Data 4 282.97 274.35 – –
4 Data 1 291.12 271.67 – –
4 Data 2 269.61 264.97 – –
4 Data 4 271.67 267.02 – –
1 Priority 2 – – 287.69 252.33
1 Priority 4 – – 271.59 283.77
4 Priority 2 – – 259.61 288.1
4 Priority 4 – – 337.5 272.33
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