Visible to Intel only — GUID: iga1443129692702
Ixiasoft
Visible to Intel only — GUID: iga1443129692702
Ixiasoft
31.7.1.3. Descriptor Format
The mSGDMA without the Prefetcher core defines two types of descriptor formats. Standard descriptor format which consists of 128 bits and extended descriptor format which consists of 256 bits. With the Prefetcher core enabled, the existing descriptor format is expanded to 256 bits and 512 bits respectively in order to accommodate additional control information for the prefetcher operation.
Byte Lanes | ||||
Offset | 3 | 2 | 1 | 0 |
0x0 | Read Address [31-0] | |||
0x4 | Write Address [31-0] | |||
0x8 | Length [31-0] | |||
0xC | Next Desc Ptr [31-0] | |||
0x10 | Actual Bytes Transferred [31-0] | |||
0x14 | Reserved [15-0] | Status [15-0] | ||
0x18 | Reserved [31-0] | |||
0x1C | Control [31, 30, 29..0] |
Byte Lanes | ||||
Offset | 3 | 2 | 1 | 0 |
0x0 | Read Address [31-0] | |||
0x4 | Write Address [31-0] | |||
0x8 | Length [31-0] | |||
0xC | Next Desc Ptr [31-0] | |||
0x10 | Actual Bytes Transferred [31-0] | |||
0x14 | Reserved [15-0] | Status [15-0] | ||
0x18 | Reserved [31-0] | |||
0x1C | Write Burst Count [7-0] | Read Burst Count [7-0] | Sequence Number [15-0] | |
0x20 | Write Stride [15-0] | Read Stride [15-0] | ||
0x24 | Read Address [63-32] | |||
0x28 | Write Address [63-32] | |||
0x2C | Next Desc Ptr [63-32] | |||
0x30 | Reserved [31-0] | |||
0x34 | Reserved [31-0] | |||
0x38 | Reserved [31-0] | |||
0x3C | Control [31, 30, 29..0] |