A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: iga1401396179699
Ixiasoft
Visible to Intel only — GUID: iga1401396179699
Ixiasoft
2.3.1. Interfaces
Avalon® -ST Interfaces
The core includes Avalon® -ST interfaces for transferring data and almost-full status.
Feature | Property | |
---|---|---|
Data Interfaces | Status Interfaces | |
Backpressure | Ready latency = 0. | Not supported. |
Data Width | Configurable. | Data width = 2 bits. Symbols per beat = 1. |
Channel | Supported, up to 16 channels. | Supported, up to 16 channels. |
Error | Configurable. | Not used. |
Packet | Supported. | Not supported. |
Avalon® -MM Interfaces
The core can have up to three Avalon® -MM interfaces:
- Avalon® -MM control interface—Allows host peripherals to set and access almost-full and almost-empty thresholds. The same set of thresholds is used by all channels. See Control Interface Register Map figure for the description of the threshold registers.
- Avalon® -MM fill-level interface—Allows host peripherals to retrieve the fill level of the FIFO buffer for a given channel. The fill level represents the amount of data in the FIFO buffer at any given time. The read latency on this interface is one. See the Fill-level Interface Register Map table for the description of the fill-level registers.
- Avalon® -MM request interface—Allows host peripherals to request data for a given channel. This interface is implemented only when the Use Request parameter is turned on. The request_address signal contains the channel number. Only one word of data is returned for each request.
For more information about Avalon® interfaces, refer to the Avalon® Interface Specifications.