A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: uaw1575498496002
Ixiasoft
Visible to Intel only — GUID: uaw1575498496002
Ixiasoft
50.4.1. Clocking Scheme
Either the PHY or an external source supplies a fixed 50 MHz reference clock to the IP core. The IP core instantiates two internal clock dividers which generates the required clocks for transmitter and receiver to support 100 Mbps and 10Mbps speed modes.
There are two division by 2-clock divider and one division by 10-clock divider.
- 25 MHz for IP core to MII MAC transmit clock for 100 Mbps data rate
- 2.5 MHz for IP core to MII MAC transmit clock for 10 Mbps data rate
- 5 MHz for RMII PHY to IP core receive clock for 10 Mbps data rate