Intel® Quartus® Prime Pro Edition User Guide: Third-party Synthesis

ID 683122
Date 3/28/2022
Public

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2.10.1. Instantiating Intel FPGA IP Cores with the IP Catalog

When you use the IP Catalog and Parameter Editor to set up and configure an IP core, the IP Catalog creates a VHDL or Verilog HDL wrapper file <output file>.v|vhd that instantiates the IP core.

The Synplify software uses the Intel® Quartus® Prime timing and resource estimation netlist feature to report more accurate resource utilization and timing performance estimates, and uses timing-driven optimization, instead of treating the IP core as a “black box.” Including the generated IP core variation wrapper file in your Synplify project, gives the Synplify software complete information about the IP core.

Note: There is an option in the Parameter Editor to generate a netlist for resource and timing estimation. This option is not recommended for the Synplify software because the software automatically generates this information in the background without a separate netlist. If you do create a separate netlist <output file>_syn.v and use that file in your synthesis project, you must also include the <output file>.v|vhd file in your Intel® Quartus® Prime project.

Verify that the correct Intel® Quartus® Prime version is specified in the Synplify software before compiling the generated file to ensure that the software uses the correct library definitions for the IP core. The Quartus Version setting must match the version of the Intel® Quartus® Prime software used to generate the customized IP core.

In addition, ensure that the QUARTUS_ROOTDIR environment variable specifies the installation directory location of the correct Intel® Quartus® Prime version. The Synplify software uses this information to launch the Intel® Quartus® Prime software in the background. The environment variable setting must match the version of the Intel® Quartus® Prime software used to generate the customized IP core.