Visible to Intel only — GUID: ouf1720662993458
Ixiasoft
1.2.1. RAM: 2-PORT FPGA IP v20.5.0
1.2.2. RAM: 2-PORT Intel® FPGA IP v20.4.1
1.2.3. RAM: 2-PORT Intel® FPGA IP v20.4.0
1.2.4. RAM: 2-PORT Intel® FPGA IP v20.2.0
1.2.5. RAM: 2-PORT Intel® FPGA IP v20.1.0
1.2.6. RAM: 2-PORT Intel® FPGA IP v20.0.0
1.2.7. RAM: 2-PORT Intel® FPGA IP v19.2.0
1.2.8. RAM: 2-PORT Intel® FPGA IP v19.1
1.2.9. RAM: 2-PORT Intel® FPGA IP v18.1
1.2.10. RAM: 2-PORT Intel® FPGA IP v18.0
1.4.1. ROM: 1-PORT FPGA IP v20.2.2
1.4.2. ROM: 1-PORT Intel® FPGA IP v20.2.1
1.4.3. ROM: 1-PORT Intel® FPGA IP v20.2.0
1.4.4. ROM: 1-PORT Intel® FPGA IP v20.1.0
1.4.5. ROM: 1-PORT Intel® FPGA IP v20.0.0
1.4.6. ROM: 1-PORT Intel® FPGA IP v19.2.0
1.4.7. ROM: 1-PORT Intel® FPGA IP v19.1
1.4.8. ROM: 1-PORT Intel® FPGA IP v18.0
Visible to Intel only — GUID: ouf1720662993458
Ixiasoft
1.1.1. RAM: 2-PORT Intel® FPGA IP v20.5.0
Quartus® Prime Version | Description | Impact |
---|---|---|
24.2 | Allows "NEW_DATA" behavior for mixed-port read-during-write in true dual port (TDP) mode for M20K block. | This change is optional. If you do not upgrade your IP, it does not have this new feature. |