Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT

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Date 4/07/2025
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1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT
1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT x
1.1. RAM: 1-PORT 1.2. RAM: 2-PORT 1.3. RAM: 4-PORT 1.4. ROM: 1-PORT 1.5. ROM: 2-PORT
1.1. RAM: 1-PORT x
1.1.1. RAM: 1-PORT FPGA IP v20.1.1 1.1.2. RAM: 1-PORT Intel® FPGA IP v20.1.0 1.1.3. RAM: 1-PORT Intel® FPGA IP v20.0.0 1.1.4. RAM: 1-PORT Intel® FPGA IP v19.2.0 1.1.5. RAM: 1-PORT Intel® FPGA IP v18.0
1.2. RAM: 2-PORT x
1.2.1. RAM: 2-PORT FPGA IP v20.5.0 1.2.2. RAM: 2-PORT Intel® FPGA IP v20.4.1 1.2.3. RAM: 2-PORT Intel® FPGA IP v20.4.0 1.2.4. RAM: 2-PORT Intel® FPGA IP v20.2.0 1.2.5. RAM: 2-PORT Intel® FPGA IP v20.1.0 1.2.6. RAM: 2-PORT Intel® FPGA IP v20.0.0 1.2.7. RAM: 2-PORT Intel® FPGA IP v19.2.0 1.2.8. RAM: 2-PORT Intel® FPGA IP v19.1 1.2.9. RAM: 2-PORT Intel® FPGA IP v18.1 1.2.10. RAM: 2-PORT Intel® FPGA IP v18.0
1.3. RAM: 4-PORT x
1.3.1. RAM: 4-PORT FPGA IP v20.1.1 1.3.2. RAM: 4-PORT Intel® FPGA IP v20.1.0 1.3.3. RAM: 4-PORT Intel® FPGA IP v20.0.0 1.3.4. RAM: 4-PORT Intel® FPGA IP v19.2.0 1.3.5. RAM: 4-PORT Intel® FPGA IP v19.1 1.3.6. RAM: 4-PORT Intel® FPGA IP v18.0
1.4. ROM: 1-PORT x
1.4.1. ROM: 1-PORT FPGA IP v20.2.2 1.4.2. ROM: 1-PORT Intel® FPGA IP v20.2.1 1.4.3. ROM: 1-PORT Intel® FPGA IP v20.2.0 1.4.4. ROM: 1-PORT Intel® FPGA IP v20.1.0 1.4.5. ROM: 1-PORT Intel® FPGA IP v20.0.0 1.4.6. ROM: 1-PORT Intel® FPGA IP v19.2.0 1.4.7. ROM: 1-PORT Intel® FPGA IP v19.1 1.4.8. ROM: 1-PORT Intel® FPGA IP v18.0
1.5. ROM: 2-PORT x
1.5.1. ROM: 2-PORT FPGA IP v20.1.1 1.5.2. ROM: 2-PORT Intel® FPGA IP v20.1.0 1.5.3. ROM: 2-PORT Intel® FPGA IP v20.0.0 1.5.4. ROM: 2-PORT Intel® FPGA IP v19.2.0 1.5.5. ROM: 2-PORT Intel® FPGA IP v18.1 1.5.6. ROM: 2-PORT Intel® FPGA IP v18.0
1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT

1.5.2. RAM: 2-PORT Intel® FPGA IP v20.2.0

Table 8.  v20.2.0 2021.06.29
Quartus® Prime Version Description Impact
20.3 Fixed the unconnected byteena port for MLAB RAM block type without read address registered when using the byte enable feature. The change is optional. You are required to perform IP upgrade if you have this configuration to ensure that the byteena port is correctly connected.
Table 9.  v20.2.0 2020.10.12
Quartus® Prime Version Description Impact
20.3 Removed support for the Use Stratix M512 emulation logic cell style for the LCs memory block type option for Stratix® 10 and Agilex™ 7 devices. You are required to either change to default logic cell style or switch to non-LCs memory block type.
Removed the Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time. option for Stratix® 10 and Agilex™ 7 devices. You are required to perform IP upgrade if you set the option to false (default is true).
Updated the following parameter settings tab names:
  • Output 1 to Mixed Port Read-During-Write
  • Output 2 to Same Port Read-During-Write
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