Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT

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Date 8/04/2025
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1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT
1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT x
1.1. RAM: 1-PORT 1.2. RAM: 2-PORT 1.3. RAM: 4-PORT 1.4. ROM: 1-PORT 1.5. ROM: 2-PORT
1.1. RAM: 1-PORT x
1.1.1. RAM: 1-PORT FPGA IP v20.1.1 1.1.2. RAM: 1-PORT Intel® FPGA IP v20.1.0 1.1.3. RAM: 1-PORT Intel® FPGA IP v20.0.0 1.1.4. RAM: 1-PORT Intel® FPGA IP v19.2.0 1.1.5. RAM: 1-PORT Intel® FPGA IP v18.0
1.2. RAM: 2-PORT x
1.2.1. RAM: 2-PORT FPGA IP v20.6.0 1.2.2. RAM: 2-PORT FPGA IP v20.5.0 1.2.3. RAM: 2-PORT Intel® FPGA IP v20.4.1 1.2.4. RAM: 2-PORT Intel® FPGA IP v20.4.0 1.2.5. RAM: 2-PORT Intel® FPGA IP v20.2.0 1.2.6. RAM: 2-PORT Intel® FPGA IP v20.1.0 1.2.7. RAM: 2-PORT Intel® FPGA IP v20.0.0 1.2.8. RAM: 2-PORT Intel® FPGA IP v19.2.0 1.2.9. RAM: 2-PORT Intel® FPGA IP v19.1 1.2.10. RAM: 2-PORT Intel® FPGA IP v18.1 1.2.11. RAM: 2-PORT Intel® FPGA IP v18.0
1.3. RAM: 4-PORT x
1.3.1. RAM: 4-PORT FPGA IP v20.1.1 1.3.2. RAM: 4-PORT Intel® FPGA IP v20.1.0 1.3.3. RAM: 4-PORT Intel® FPGA IP v20.0.0 1.3.4. RAM: 4-PORT Intel® FPGA IP v19.2.0 1.3.5. RAM: 4-PORT Intel® FPGA IP v19.1 1.3.6. RAM: 4-PORT Intel® FPGA IP v18.0
1.4. ROM: 1-PORT x
1.4.1. ROM: 1-PORT FPGA IP v20.2.2 1.4.2. ROM: 1-PORT Intel® FPGA IP v20.2.1 1.4.3. ROM: 1-PORT Intel® FPGA IP v20.2.0 1.4.4. ROM: 1-PORT Intel® FPGA IP v20.1.0 1.4.5. ROM: 1-PORT Intel® FPGA IP v20.0.0 1.4.6. ROM: 1-PORT Intel® FPGA IP v19.2.0 1.4.7. ROM: 1-PORT Intel® FPGA IP v19.1 1.4.8. ROM: 1-PORT Intel® FPGA IP v18.0
1.5. ROM: 2-PORT x
1.5.1. ROM: 2-PORT FPGA IP v20.1.1 1.5.2. ROM: 2-PORT Intel® FPGA IP v20.1.0 1.5.3. ROM: 2-PORT Intel® FPGA IP v20.0.0 1.5.4. ROM: 2-PORT Intel® FPGA IP v19.2.0 1.5.5. ROM: 2-PORT Intel® FPGA IP v18.1 1.5.6. ROM: 2-PORT Intel® FPGA IP v18.0
1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT

1.4.4. ROM: 1-PORT Intel® FPGA IP v20.1.0

Table 37.  v20.1.0 2020.10.12
Quartus® Prime Version Description Impact
20.3

Removed support for Use Stratix M512 emulation logic cell style for the LCs memory block type in the Stratix® 10 and Agilex™ 7 devices.

 You are required to either change to default logic cell style or switch to non-LCs memory block type in the Stratix® 10 and Agilex™ 7 devices.
Added "X" propagation support in simulation model for the Stratix® 10 devices. —
Table 38.  v20.1.0 2020.08.03
Quartus® Prime Version Description Impact
20.1 Enabled the In-System Memory Content Editor (ISMCE) support in the Agilex™ 7 devices. This change is optional. If you do not upgrade your IP, it does not have this new feature.
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