Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT

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ID 683110
Date 8/04/2025
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1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT
1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT x
1.1. RAM: 1-PORT 1.2. RAM: 2-PORT 1.3. RAM: 4-PORT 1.4. ROM: 1-PORT 1.5. ROM: 2-PORT
1.1. RAM: 1-PORT x
1.1.1. RAM: 1-PORT FPGA IP v20.1.1 1.1.2. RAM: 1-PORT Intel® FPGA IP v20.1.0 1.1.3. RAM: 1-PORT Intel® FPGA IP v20.0.0 1.1.4. RAM: 1-PORT Intel® FPGA IP v19.2.0 1.1.5. RAM: 1-PORT Intel® FPGA IP v18.0
1.2. RAM: 2-PORT x
1.2.1. RAM: 2-PORT FPGA IP v20.6.0 1.2.2. RAM: 2-PORT FPGA IP v20.5.0 1.2.3. RAM: 2-PORT Intel® FPGA IP v20.4.1 1.2.4. RAM: 2-PORT Intel® FPGA IP v20.4.0 1.2.5. RAM: 2-PORT Intel® FPGA IP v20.2.0 1.2.6. RAM: 2-PORT Intel® FPGA IP v20.1.0 1.2.7. RAM: 2-PORT Intel® FPGA IP v20.0.0 1.2.8. RAM: 2-PORT Intel® FPGA IP v19.2.0 1.2.9. RAM: 2-PORT Intel® FPGA IP v19.1 1.2.10. RAM: 2-PORT Intel® FPGA IP v18.1 1.2.11. RAM: 2-PORT Intel® FPGA IP v18.0
1.3. RAM: 4-PORT x
1.3.1. RAM: 4-PORT FPGA IP v20.1.1 1.3.2. RAM: 4-PORT Intel® FPGA IP v20.1.0 1.3.3. RAM: 4-PORT Intel® FPGA IP v20.0.0 1.3.4. RAM: 4-PORT Intel® FPGA IP v19.2.0 1.3.5. RAM: 4-PORT Intel® FPGA IP v19.1 1.3.6. RAM: 4-PORT Intel® FPGA IP v18.0
1.4. ROM: 1-PORT x
1.4.1. ROM: 1-PORT FPGA IP v20.2.2 1.4.2. ROM: 1-PORT Intel® FPGA IP v20.2.1 1.4.3. ROM: 1-PORT Intel® FPGA IP v20.2.0 1.4.4. ROM: 1-PORT Intel® FPGA IP v20.1.0 1.4.5. ROM: 1-PORT Intel® FPGA IP v20.0.0 1.4.6. ROM: 1-PORT Intel® FPGA IP v19.2.0 1.4.7. ROM: 1-PORT Intel® FPGA IP v19.1 1.4.8. ROM: 1-PORT Intel® FPGA IP v18.0
1.5. ROM: 2-PORT x
1.5.1. ROM: 2-PORT FPGA IP v20.1.1 1.5.2. ROM: 2-PORT Intel® FPGA IP v20.1.0 1.5.3. ROM: 2-PORT Intel® FPGA IP v20.0.0 1.5.4. ROM: 2-PORT Intel® FPGA IP v19.2.0 1.5.5. ROM: 2-PORT Intel® FPGA IP v18.1 1.5.6. ROM: 2-PORT Intel® FPGA IP v18.0
1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT

1. Embedded Memory FPGA IPs Release Notes: RAM: 1-PORT, RAM: 2-PORT, RAM: 4-PORT, ROM: 1-PORT, and ROM: 2-PORT

If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Quartus® Prime Design Suite Update Release Notes.

Altera® FPGA IP versions match the Quartus® Prime Design Suite software versions until v19.1. Starting in Quartus® Prime Design Suite software version 19.2, the IP has a new versioning scheme.

The IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:

  • X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Section Content
RAM: 1-PORT
RAM: 2-PORT
RAM: 4-PORT
ROM: 1-PORT
ROM: 2-PORT

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