5G LDPC Intel® FPGA IP User Guide

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ID 683107
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC Intel® FPGA IP 4. 5G LDPC Intel® FPGA IP Functional Description 5. Parameter Optimization for the 5G LDPC IP 6. 5G LDPC IP User Guide Archive 7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide
1. About the 5G LDPC Intel® FPGA IP x
1.1. 5G LDPC Intel® FPGA IP Features 1.2. 5G LDPC Intel® FPGA IP Device Family Support 1.3. 5G LDPC IP Release Information 1.4. 5G LDPC IP Performance and Resource Utilization
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC IP IP Timeout Behavior
3. Designing with the 5G LDPC Intel® FPGA IP x
3.1. Generating a 5G LDPC Intel® FPGA IP 3.2. Simulating the 5G LDPC IP RTL 3.3. 5G LDPC Simulation Results
4. 5G LDPC Intel® FPGA IP Functional Description x
4.1. 5G LDPC Decoder 4.2. 5G LDPC Encoder 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP
4.1. 5G LDPC Decoder x
4.1.1. 5G LDPC Decoder Signals 4.1.2. 5G LDPC Decoder Data Formats 4.1.3. 5G LDPC IP Decoder Parameters
4.2. 5G LDPC Encoder x
4.2.1. 5G LDPC Encoder Signals 4.2.2. 5G LDPC Encoder Data Formats
5. Parameter Optimization for the 5G LDPC IP x
5.1. C++ and MATLAB Software Models
5.1. C++ and MATLAB Software Models x
5.1.1. Running the 5G LDPC IP C++ Models 5.1.2. Running the 5G LDPC Decoder and Encoder MATLAB Model in the Design Example
1. About the 5G LDPC Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC Intel® FPGA IP
4. 5G LDPC Intel® FPGA IP Functional Description
5. Parameter Optimization for the 5G LDPC IP
6. 5G LDPC IP User Guide Archive
7. Document Revision History for the 5G LDPC Intel® FPGA IP User Guide

1.4. 5G LDPC IP Performance and Resource Utilization

Intel generated the resource utilization and performance for the encoder and the decoder by compiling the designs with Intel Quartus Prime software v21.1 (23.2.1 for Agilex™ 5 devices). Only use these approximate results for early estimation of FPGA resources (e.g. adaptive logic modules (ALMs)) that a project requires.

Decoder

Table 2.  Resource Utilization and Maximum Frequency for Agilex™ 5 DevicesTargeting A5EC065BB32AE5SR0 device. The fMAX is the five-seeds average fMAX reduced 15% for margins.
IN_WIDTH NUM_DECODER MAX_LF_DECODER0 MAX_LF_DECODER1 ALMs M20K Memory Blocks fMAX (MHz)
6 1 384 - 53,980 762 298
Table 3.  Resource Utilization and Maximum Frequency for Agilex™ 7 DevicesTargeting AGFB014R24B2I2V device. The fMAX is the five-seeds average fMAX reduced 15% for margins.
IN_WIDTH NUM_DECODER MAX_LF_DECODER0 MAX_LF_DECODER1 ALMs M20K Memory Blocks fMAX (MHz)
6 1 384 - 58,720 762 548
6 1 192 - 30,082 402 572
6 1 128 - 19,898 281 574
6 1 96 - 15,604 221 574
6 2 - 192 88,696 1165 556
6 2 - 128 78,828 1044 549
6 2 - 96 74,520 984 550
5 1 384 - 53,588 677 561
5 1 192 - 27,420 367 572
5 1 128 - 18,314 258 577
5 1 96 - 14,134 203 576
5 2 - 192 80,494 1045 555
5 2 - 128 71,751 936 541
5 2 - 96 67,565 881 547
Table 4.  Resource Utilization and Maximum Frequency for Arria® 10 DevicesTargeting 10AT115S1F45E1SG device. The fMAX is the five-seeds average fMAX reduced 15% for margins.
IN_WIDTH NUM_DECODER MAX_LF_DECODER0 MAX_LF_DECODER1 ALMs M20K Memory Blocks fMAX (MHz)
6 1 384 - 47,261 762 306
6 1 192 - 24,698 402 339
6 1 128 - 17,015 281 348
6 1 96 - 13,381 221 360
6 2 - 192 72,690 1165 290
6 2 - 128 64,925 1044 294
6 2 - 96 61,238 984 296
5 1 384 - 41,906 677 312
5 1 192 - 21,654 367 339
5 1 128 - 15,036 258 353
5 1 96 - 11,842 203 353
5 2 - 192 63,292 1045 305
5 2 - 128 56,714 936 313
5 2 - 96 53,658 881 318
Table 5.  Resource Utilization and Maximum Frequency for Stratix® 10 DevicesTargeting 1SG280HU2F50E2VG device. The fMAX is the five-seeds average fMAX reduced 15% for margins.
IN_WIDTH NUM_DECODER MAX_LF_DECODER0 MAX_LF_DECODER1 ALMs M20K Memory Blocks fMAX (MHz)
6 1 384 - 62,090 762 384
6 1 192 - 31,889 402 413
6 1 128 - 21,772 281 409
6 1 96 - 16,838 221 419
6 2 - 192 93,439 1165 365
6 2 - 128 83,526 1044 365
6 2 - 96 79,157 984 374
5 1 384 - 56,806 677 369
5 1 192 - 29,469 367 412
5 1 128 - 20,063 258 411
5 1 96 - 15,690 203 433
5 2 - 192 84,685 1045 378
5 2 - 128 75,905 936 383
5 2 - 96 71,549 881 373
Table 6.  Resource Utilization and Maximum Frequency for Stratix® 10-L DevicesTargeting 1SG280HU2F50E2LG device. The fMAX is the five-seeds average fMAX reduced 15% for margins.
IN_WIDTH NUM_DECODER MAX_LF_DECODER0 MAX_LF_DECODER1 ALMs M20K Memory Blocks fMAX (MHz)
6 1 384 - 62,297 762 379
6 1 192 - 31,849 402 394
6 1 128 - 21,715 281 403
6 1 96 - 16,812 221 405
6 2 - 192 93,144 1165 359
6 2 - 128 83,298 1044 360
6 2 - 96 78,968 984 368
5 1 384 - 56,768 677 378
5 1 192 - 28,754 367 403
5 1 128 - 20,038 258 401
5 1 96 - 15,684 203 399
5 2 - 192 85,326 1045 367
5 2 - 128 76,386 936 381
5 2 - 96 71,937 881 367

Encoder

Intel generated the data for the following devices:

  • Intel Agilex 5 A5EC065BB32AE5SR0
  • Agilex™ 7 AGFA014R24A2E2VR0
  • Intel Arria 10 10AT115S1F45E1SG
  • Intel Stratix 10 1SG280HU2F50E2VG
  • Intel Stratix 10-L 1SG280HU2F50E2LG
Table 7.  Resource Utilization and Maximum Frequency The fMAX is the five-seeds average fMAX reduced 15% for margins.
Device ALMs M20K Memory Blocks fMAX (MHz)
A5EC065BB32AE5SR0 17,040 23 400
AGFA014R24A2E2VR0 17,684 23 554
10AT115S1F45E1SG 16,876 23 323
1SG280HU2F50E2VG 17,617 23 442
1SG280HU2F50E2LG 17,585 23 382
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