AN 736: Nios II Processor Booting From Altera Serial Flash (EPCQ)

ID 683104
Date 5/20/2016
Public

1.5.1. Design

  1. Create your Nios® II processor project using Quartus II and Qsys.
  2. Add the Intel® Serial Flash Controller IP to your Qsys system. Refer to the diagram below for the IP connection in Qsys.
    Figure 3. Altera Serial Flash Controller IP Connections in Qsys
    Note: The maximum input clock for Intel® Serial Flash Controller IP is 25 MHz. The input clock must not exceed this maximum value.