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1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Recommended HDL Coding Styles Revision History
22.214.171.124. Use Synchronous Memory Blocks 126.96.36.199. Avoid Unsupported Reset and Control Conditions 188.8.131.52. Check Read-During-Write Behavior 184.108.40.206. Controlling RAM Inference and Implementation 220.127.116.11. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 18.104.22.168. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 22.214.171.124. Simple Dual-Port, Dual-Clock Synchronous RAM 126.96.36.199. True Dual-Port Synchronous RAM 188.8.131.52. Mixed-Width Dual-Port RAM 184.108.40.206. RAM with Byte-Enable Signals 220.127.116.11. Specifying Initial Memory Contents at Power-Up
18.104.22.168. If Performance is Important, Optimize for Speed 22.214.171.124. Use Separate CRC Blocks Instead of Cascaded Stages 126.96.36.199. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 188.8.131.52. Take Advantage of Latency if Available 184.108.40.206. Save Power by Disabling CRC Blocks When Not in Use 220.127.116.11. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
1.6.8. Counter HDL Guidelines
The Intel® Quartus® Prime synthesis engine implements counters in HDL code as an adder followed by registers, and makes available register control signals such as enable (ena), synchronous clear (sclr), and synchronous load (sload). For best area utilization, ensure that the up and down control or controls are expressed in terms of one addition operator, instead of two separate addition operators.
If you use the following coding style, your synthesis engine may implement two separate carry chains for addition:
out <= count_up ? out + 1 : out - 1;
For simple designs, the synthesis engine identifies this coding style and optimizes the logic. However, in complex designs, or designs with preserve pragmas, the Compiler cannot optimize all logic, so more careful coding becomes necessary.
The following coding style requires only one adder along with some other logic:
out <= out + (count_up ? 1 : -1);
This style makes more efficient use of resources and area, since it uses only one carry chain adder, and the –1 constant logic is implemented in the LUT before the adder.
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