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1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Recommended HDL Coding Styles Revision History
220.127.116.11. Use Synchronous Memory Blocks 18.104.22.168. Avoid Unsupported Reset and Control Conditions 22.214.171.124. Check Read-During-Write Behavior 126.96.36.199. Controlling RAM Inference and Implementation 188.8.131.52. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 184.108.40.206. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 220.127.116.11. Simple Dual-Port, Dual-Clock Synchronous RAM 18.104.22.168. True Dual-Port Synchronous RAM 22.214.171.124. Mixed-Width Dual-Port RAM 126.96.36.199. RAM with Byte-Enable Signals 188.8.131.52. Specifying Initial Memory Contents at Power-Up
184.108.40.206. If Performance is Important, Optimize for Speed 220.127.116.11. Use Separate CRC Blocks Instead of Cascaded Stages 18.104.22.168. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 22.214.171.124. Take Advantage of Latency if Available 126.96.36.199. Save Power by Disabling CRC Blocks When Not in Use 188.8.131.52. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
184.108.40.206. Use Synchronous Clock Enables
To turn off a clock domain in a synchronous manner, use a synchronous clock enable signal. FPGAs efficiently support clock enable signals because there is a dedicated clock enable signal available on all device registers.
This scheme does not reduce power consumption as much as gating the clock at the source because the clock network keeps toggling, and performs the same function as a gated clock by disabling a set of registers. Insert a multiplexer in front of the data input of every register to either load new data, or copy the output of the register.
Figure 14. Synchronous Clock Enable
When designing for Intel® Stratix® 10 devices, consider that high fan-out clock enable signals can limit the performance achievable by the Hyper- Retimer. For specific recommendations, refer to the Intel® Stratix® 10 High-Performance Design Handbook.
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